Projects

Master's Thesis

GEMM Accelerator on Cyclone V SoC

Custom RTL matrix-multiply accelerator taken from SystemVerilog through Qsys integration to a full Linux bring-up (custom kernel, device-tree overlay, UIO binding, and user-space driver). An 8x8 heterogeneous systolic array runs INT8/INT16/INT32/FP16/FP32 in one multi-precision MAC. Fitter shows 112/112 DSP at 48% ALMs; a wide-port DMA fast path, operand-locality tuning (resident A, double-buffered B), and a hardware tile-row batch sequencer walk memory stall down 93% to 76% to 19% and take INT8 512^3 to 3.15 GOP/s at 50 MHz, about 27x an ARM A9 software reference, at 60% compute occupancy, bit-exact across all precisions (60/60 on-board tests).

SystemVerilog · FPGA · Cyclone V SoC · Linux driver · DSP

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Analog / RF IC Design

CMOS Power Amplifier for GSM

Two-stage Class-AB power amplifier in TSMC 0.18um RF CMOS, designed in Cadence Virtuoso/SpectreRF with load-pull optimization. Targets the commercial Qorvo RF5110G and, in simulation, exceeds it: +38 dBm PSAT, 64.2% peak PAE, 33.2 dB gain, Ft of 26 GHz, with a 57% projected die-cost reduction versus GaAs HBT. (Simulation results, not silicon-measured.)

RF CMOS · Cadence Virtuoso · SpectreRF · Load-pull · 0.18um

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CMOS Ring Oscillator (0.18um)

Five-stage transistor-level ring oscillator in the IBM 0.18um (cmrf7sf) CMOS process, designed, simulated, and laid out in Cadence Virtuoso. Met the 1 GHz +/- 100 MHz target (measured 1.06 GHz at N=5, Wn=82um, Wp=264um, Vdd=1.33V) with a DRC/LVS-clean layout.

0.18um CMOS · Cadence Virtuoso · DRC/LVS · Layout · Transient sim

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Digital Design & FPGA

NES Emulator on FPGA

Cycle-aware NES emulator in Verilog built around a 6502 core, with custom PPU, APU, and VGA modules for video and audio. A UART path loads game ROMs and reads joystick input; memory-mapping logic handles cartridge data. Verified in Vivado/ISE and ModelSim for sprite rendering, frame rate, and audio sync.

Verilog · 6502 · PPU/APU · VGA · Vivado

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SystemVerilog Programmable Processor

Programmable CPU in SystemVerilog (TCES330 course project). A control unit (instruction memory, program counter, instruction register, and FSM) drives a datapath (register file, ALU, data memory, and a 2:1 mux), tied together in a top-level processor. Executes NOOP/STORE/LOAD/ADD/SUB/HALT, runs on an FPGA with 7-segment output, and is verified with module and processor testbenches.

SystemVerilog · CPU · FSM · FPGA · Verification

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Computer Architecture & Systems Software

Three-Level Cache Simulator

C++ simulator for an L1/L2/L3 hierarchy with configurable associativity, line size, and replacement policy (LRU/FIFO). Compared inclusive vs non-inclusive policies and a 12-entry victim cache on real trace files: improved AMAT from 7.64 to 4.80 cycles and L2 hit rate from ~23% to ~57%.

C++ · Caches · AMAT · Trace-driven · LRU/FIFO

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Game Boy Advance Emulator

Emulator in C targeting a cycle-accurate ARM7TDMI core, written to deepen computer-architecture and systems-programming skills after building Game Boy and Game Boy Color emulators.

C · ARM7TDMI · Emulation · Cycle-accurate

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Linux Kernel I2C Driver

Kernel-space board support and an I2C driver for a Raspberry Pi peripheral, exercised from user space through syscalls. Hands-on practice with the Linux driver model, device interfaces, and the kernel/user boundary.

Linux kernel · I2C · BSP · Device drivers · C

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Embedded Systems & Control

Quadcopter Flight Controller Firmware

Bare-metal firmware on an STM32F405 (ARM Cortex-M4) with a custom lightweight RTOS and ExpressLRS (LoRa) telemetry. A dual-rate lifted-model GPC state-space controller fuses an ICM20602 (1200 Hz) and a BNO085 (400 Hz) through a Kalman filter; in MATLAB/Simulink it roughly halved RMS tracking error versus a double/inner-loop PID (0.06 to 0.03) with faster settling (0.8 s vs 1.2 s) and lower overshoot (5% vs 12%). Brought up on a custom v1 PCB.

STM32 · Cortex-M4 · Custom RTOS · Kalman filter · GPC control

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Model Predictive Control Rover

Autonomous rover using sonar and an MPU6050 IMU with real-time Model Predictive Control for obstacle avoidance. STM32 (custom RTOS) drives the motors while an ESP32 (FreeRTOS) runs the Hildreth constrained-optimization solver and a Wi-Fi telemetry server, cutting avoidance response time 30% over the prior PID rover.

STM32 · ESP32 · MPC · Hildreth · FreeRTOS

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Wildlife UWB Tracking (Senior Capstone)

Capstone with the Washington Department of Fish and Wildlife and Texas Instruments: custom ultra-wideband PCBs track endangered turtles, and a relay device computes position and texts biologists when a turtle leaves its pond. PCB design mentored by TI engineers in Altium, replacing manual radio triangulation.

UWB · Custom PCB · Altium · Embedded · WDFW + TI

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Autonomous Obstacle-Avoidance Rover

Team rover on a TI TM4C (ARM Cortex-M4) that uses sonar to detect obstacles within a meter and steers around them. Bluetooth/UART control and PWM motor drive, developed and tested in Keil uVision.

TM4C · Cortex-M4 · Sonar · PWM · Keil

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Tools & Applied Computing

vSchem Schematic Editor

Cross-platform engineering notepad and schematic editor on a Vulkan/WebGPU C++ core. Combines freehand ink notes with drag-and-drop circuit design and KCL/KVL/MNA analysis, targeting iPad, Android, web, and desktop.

C++ · Vulkan/WebGPU · MNA solver · EDA · Cross-platform

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Image Filtering Techniques

Comparative study of Gaussian blur, median filtering, and Sobel edge detection in C++ with OpenCV, analyzed in MATLAB. Measured noise reduction, edge preservation, and runtime trade-offs to guide filter selection.

C++ · OpenCV · MATLAB · DSP · Image processing

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