A CMOS Power Amplifier for GSM (Simulation Study)
Post by Souleymane Dembele on Jun 15, 2025
For my wireless IC design course (TECE 523), I designed a GSM-band power amplifier in TSMC 0.18um RF CMOS and compared it in simulation against a commercial part, the Qorvo RF5110G GaAs HBT amplifier. The goal was to show that careful CMOS design can rival GaAs performance while keeping the cost and integration advantages of a standard CMOS process. All results below are from Cadence SpectreRF simulation with post-layout extraction; this design was not taped out or silicon-measured.
Approach
I used a two-stage cascaded Class-AB topology: a Class-A/AB driver for linearity followed by a Class-AB output stage for efficiency, sized for 33 dB of gain. Power stage devices are a 64x30um finger array for thermal spreading; the driver is a 16x30um array. The design work was done in Cadence Virtuoso with SpectreRF, using PSS for large-signal behavior, PAC for small-signal gain, and load-pull and source-pull sweeps to find the optimal impedances. Matching networks transform 50 ohm down to the roughly 1-2 ohm optimal load with multi-section L-C networks, optimized for inductor Q.
Results vs the target (SpectreRF simulation)
| Parameter | Qorvo RF5110G | This design (simulated) |
|---|---|---|
| Output power (PSAT) | +35 dBm | +38.0 dBm |
| Power-added efficiency | 55% | 64.2% |
| Power gain | 32 dB | 33.2 dB |
| Transition frequency (Ft) | 15 GHz | 26 GHz |
| P1dB | n/a | +34 dBm |
| Technology | GaAs HBT | 0.18um RF CMOS |
The design is unconditionally stable (K-factor 1.35), meets the GSM900 spectral mask with second and third harmonics below -40 dBc, and a die-cost analysis projects a 57% manufacturing-cost reduction versus the GaAs part.
What I took from it
This was full custom analog/RF design at the transistor and layout level: device sizing for high Ft, load-pull-driven matching, stability and ESD considerations, and a CAD flow from schematic through SpectreRF to a DRC/LVS-clean layout with post-extraction verification.
View the full design report (PDF) · View the design presentation (PDF)