A Programmable Processor in SystemVerilog
Post by Souleymane Dembele on Jun 06, 2023
A small programmable CPU built in SystemVerilog for a digital-system-design course (TCES 330), taken from instruction set to a working processor on an FPGA.
What it does
The processor splits cleanly into a control unit and a datapath. The control unit holds the instruction memory, a program counter, an instruction register, and a finite-state machine that sequences each instruction. The datapath holds the register file, the ALU, the data memory, and a 2:1 mux that selects whether write-back comes from the ALU or from memory. A top-level module wires the two halves together into the processor.
It executes a small instruction set, NOOP, STORE, LOAD, ADD, SUB, and HALT, runs on an FPGA with results shown on a 7-segment display, and is verified with per-module testbenches (FSM, controller, datapath) plus a full-processor bench.