A Three-Level Cache Simulator and What It Taught Me
Post by Souleymane Dembele on Dec 10, 2024
For a computer-architecture course I built a trace-driven simulator of a three-level cache hierarchy in C++ and used it to study how policy and geometry choices move real performance metrics.
What it models
The simulator implements L1, L2, and L3 caches with configurable associativity, line size, and replacement policy (LRU, FIFO, and an optimized LRU). It can run as either an inclusive or a non-inclusive hierarchy, and it optionally adds a 12-entry victim cache that captures lines recently evicted from L1. It reports miss rate, write-backs, bytes transferred, and average memory access time (AMAT) from real trace files.
Findings
| Experiment | Before | After |
|---|---|---|
| AMAT (associativity + line-size tuning) | 7.64 cycles | 4.80 cycles |
| L2 unified hit rate (non-inclusive + victim cache) | ~23% | ~57% |
Expanding cache size and associativity drove the AMAT improvement, while moving from an inclusive to a non-inclusive policy and adding the victim cache more than doubled the L2 hit rate by keeping frequently re-referenced lines on chip.
What I took from it
A concrete, measured intuition for the memory hierarchy: how inclusion policy, associativity, line size, and a victim cache trade off against each other, and how to quantify those trade-offs from traces rather than rules of thumb.