Research

My work centers on computer architecture and hardware acceleration: precision-flexible datapaths, systolic-array dataflow, and performance modeling for edge AI inference. The thread running through it is making domain-specific accelerators that stay efficient at the small problem sizes real edge workloads actually run.

Current work

My MS thesis designs a multi-precision GEMM accelerator on a Cyclone V SoC and measures the area, timing, and energy cost of precision flexibility against fixed-precision baselines, paired with a precision-aware roofline analysis. A companion study quantifies where GPUs lose efficiency at edge GEMM dimensions, the warp-scheduling, register-file, and memory-controller overheads, using GPGPU-Sim and an RTX 4090. The accelerator runs end to end on real silicon, from RTL through a full Linux bring-up. Read the accelerator case study.

Interests

Domain-specific architecture, reduced- and mixed-precision arithmetic, dataflow and memory hierarchy for accelerators, hardware/software co-design, and performance and energy modeling. I work at the intersection of hardware engineering and computer-architecture research, and I am open to hardware and accelerator engineering roles, industry research positions, and PhD programs, anywhere the work is building efficient domain-specific hardware.

Publications

CacheFormer (IEEE CCNC 2026)

An Autoformer-based predictive caching system using sparse auto-correlation to reduce attention cost to O(W log W).

view on IEEE Xplore →