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    "result": {"data":{"mdx":{"frontmatter":{"title":"A Programmable Processor in SystemVerilog","author":"Souleymane Dembele","date":"2023-06-06"},"body":"var _excluded = [\"components\"];\nfunction _extends() { return _extends = Object.assign ? Object.assign.bind() : function (n) { for (var e = 1; e < arguments.length; e++) { var t = arguments[e]; for (var r in t) ({}).hasOwnProperty.call(t, r) && (n[r] = t[r]); } return n; }, _extends.apply(null, arguments); }\nfunction _objectWithoutProperties(e, t) { if (null == e) return {}; var o, r, i = _objectWithoutPropertiesLoose(e, t); if (Object.getOwnPropertySymbols) { var s = Object.getOwnPropertySymbols(e); for (r = 0; r < s.length; r++) o = s[r], t.includes(o) || {}.propertyIsEnumerable.call(e, o) && (i[o] = e[o]); } return i; }\nfunction _objectWithoutPropertiesLoose(r, e) { if (null == r) return {}; var t = {}; for (var n in r) if ({}.hasOwnProperty.call(r, n)) { if (e.includes(n)) continue; t[n] = r[n]; } return t; }\n/* @jsxRuntime classic */\n/* @jsx mdx */\n\nvar _frontmatter = {\n  \"title\": \"A Programmable Processor in SystemVerilog\",\n  \"slug\": \"projects/programmable-processor\",\n  \"author\": \"Souleymane Dembele\",\n  \"date\": \"2023-06-06\",\n  \"isDraft\": false\n};\nvar layoutProps = {\n  _frontmatter: _frontmatter\n};\nvar MDXLayout = \"wrapper\";\nreturn function MDXContent(_ref) {\n  var components = _ref.components,\n    props = _objectWithoutProperties(_ref, _excluded);\n  return mdx(MDXLayout, _extends({}, layoutProps, props, {\n    components: components,\n    mdxType: \"MDXLayout\"\n  }), mdx(\"p\", null, \"A small programmable CPU built in SystemVerilog for a digital-system-design\\ncourse (TCES 330), taken from instruction set to a working processor on an FPGA.\"), mdx(\"h2\", null, \"What it does\"), mdx(\"p\", null, \"The processor splits cleanly into a control unit and a datapath. The control\\nunit holds the instruction memory, a program counter, an instruction register,\\nand a finite-state machine that sequences each instruction. The datapath holds\\nthe register file, the ALU, the data memory, and a 2:1 mux that selects whether\\nwrite-back comes from the ALU or from memory. A top-level module wires the two\\nhalves together into the processor.\"), mdx(\"p\", null, \"It executes a small instruction set, NOOP, STORE, LOAD, ADD, SUB, and HALT, runs\\non an FPGA with results shown on a 7-segment display, and is verified with\\nper-module testbenches (FSM, controller, datapath) plus a full-processor bench.\"), mdx(\"h2\", null, \"Links\"), mdx(\"a\", {\n    href: \"https://github.com/souleymanedembele/Project_16_bit_CPU\",\n    target: \"_blank\",\n    rel: \"noopener noreferrer\"\n  }, \"View the code on GitHub\"), \" \\xA0\\xB7\\xA0 \", mdx(\"a\", {\n    href: \"/docs/programmable-processor-report.pdf\",\n    target: \"_blank\",\n    rel: \"noopener noreferrer\"\n  }, \"View the project report (PDF)\"));\n}\n;\nMDXContent.isMDXComponent = true;"}},"pageContext":{"slug":"projects/programmable-processor"}},
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